| Project Statistics |
| PROP_Board=Spartan-6 Posedge-One Board |
PROP_Enable_Message_Filtering=false |
| PROP_FitterReportFormat=HTML |
PROP_ImpactProjectFile=changed |
| PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
| PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
| PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
| PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
| PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2017-04-23T12:35:57 |
| PROP_intWbtProjectID=DDFE9178226A4445B6180BF5303C580C |
PROP_intWbtProjectIteration=2 |
| PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
| PROP_lockPinsUcfFile=changed |
PROP_xilxBitgStart_IntDone=true |
| PROP_AutoTop=false |
PROP_DevFamily=Spartan6 |
| PROP_xilxMapEnableMultiThreading=2 |
PROP_DevDevice=xc6slx9 |
| PROP_DevFamilyPMName=spartan6 |
PROP_DevPackage=tqg144 |
| PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_parEnableMultiThreading_spartan6=4 |
| PROP_DevSpeed=-2 |
PROP_PreferredLanguage=VHDL |
| FILE_COREGEN=1 |
FILE_SCHEMATIC=1 |
| FILE_UCF=1 |
FILE_VHDL=1 |